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| * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 1 preliminary preliminary preliminary preliminary preliminary 12.16.1997 general description the EM78250/450 is an 8-bit microprocessor with low-power, high speed cmos technology. integrated onto a single chip are on-chip watchdog timer (wdt), ram, rom, real time clock/counter, power down mode and bidirectional tri-state i/o ports. it can be developed as keyboard encoder or other applications. features ? operating voltage range : 4v ~ 6v, 2v~4v option by code. ? available in temperature range: 0 c ~ 70 c. ? operating frequency range : crystal type : dc ~ 20mhz at 5v dc ~ 8mhz at 3v rc type : dc ~ 4mhz at 5v dc ~ 4mhz at 3v ? 2k x 13 on chip rom (EM78250), or 4k x 13 on chip rom (em78450) ? 11 special function registers. ? 147 8 general purpose registers (sram). ? 5 bi-directional i/o ports (35 i/o pins). ? 3 led direct sink pins with internal serial resistor, option by code. ? one interrupt pin available. ? built-in rc oscillator with external serial resistor, 10% variation. ? built-in power on reset. ? 5 level stack for subroutine nesting. ? 8-bit real time clock/counter (tcc) with overflow interrupt. ? two oscillator periods option or four oscillator periods per instruction cycle. ? power down mode. ? programmable wake up from sleep circuit on i/o ports. ? programmable free running on-chip watchdog timer. ? twelve wake-up pins. ? two open-drain pins. ? two r-option pins. ? 40 pin dip. EM78250/450 8-bit micro-controller for consumer product
* this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 2 12.16.1997 preliminary preliminary preliminary preliminary preliminary pin assignments functional block diagram v ss int data clk p90 p91 p92 p93 p94 p95 p50 p51 p52 p53 p54 p55 p56 p57 p80 p81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 osco r-osci v dd p70 p71 p72 p67 p66 p65 p64 p63 p62 p61 p60 p87 p86 p85 p84 p83 p82 EM78250/450 dip r-osci osco oscillator/timing control wdt timer wdt timeout prescaler ram r4 r1(tcc) control of sleep and wake-up on i/o ports rom instruction register instruction decoder r2 data & control bus stack alu r3 acc p50~p57 p60~p67 ioc5 r5 i/o port 5 ioc6 r6 i/o port 6 ioc7 r7 i/o port 7 ioc8 r8 i/o port 8 ioc9 r9 i/o port 9 clk, data p70~p72 p80~p87 p90~p95 interrupt control /int * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 3 preliminary preliminary preliminary preliminary preliminary 12.16.1997 symbol i/o function r-osci i xtal type : crystal output. rc type : 56 kohm 5% pull high for 1.84mhz. osco o xtal type : crystal output. rc type : clock output. p90~p95 i/o port 9 is an 6-bit bi-directional i/o port. they can be pulled-high internally by software control. p80~p87 i/o port 8 is an 8-bit bi-directional i/o port. p80 and p81 are also the r-option pins. they can be pulled-high internally by software control. p70~p72 i/o 3 led direct sink pins with internal serial register when use to do output port. option by code. clk i/o p74 and p76 connect together. p74 can be pulled-high internally by software control. p76 can have open-drain output by software control. data i/o p75 and p77 connect together . p75 can be pulled-high internally by software control. p77 can have open-drain output by software control. p60~p67 i/o port 6 is an 8-bit bi-directional port. they can be pulled-high internally by software control. p50~p57 i/o port 5 is an 8-bit bi-directional i/o port.they can be pulled-high internally by software control. vdd - power supply pin. vss - ground pin. int i falling edge schmitt triggered interrupt input pin. it indicates an interrupt if interrupt is enabled. internal pull-up resistor 50k w pin descriptions function descriptions operational registers r0 (indirect addressing register) ? r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). r1 (tcc) ? increased by the instruction cycle clock. ? written and read by the program as any other register. r2 (program counter) & stack ? depending on the device type, r2 and hardware stack are 11/12 bits wide. the structure is depicted in fig. 3. ? generates 2k/4k 13 on-chip rom addresses to the relative programming instruction codes. one program page is 1k words long. ? r2 is set all 1s upon a reset condition. ? jmp instruction allows the direct loading of the lower 10 program counter bits. thus, jmp allows jump to any location on one page. ? call instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be any location on one page. * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 4 12.16.1997 preliminary preliminary preliminary preliminary preliminary ? ret (retl k, reti) instruction loads the program counter with the contents at the top of stack. ? mov r2,a allows the loading of an address from the a register to the lower 8 bits of pc, and the ninth and tenth bits (a8~a9) of pc are cleared. ? add r2,a allows a relative address be added to the current pc, and the ninth and tenth bits of pc are cleared. ? any instruction which writes to r2 (e.g. add r2,a, mov r2,a, bc r2,6, ) (except tbl) will cause the ninth and tenth bits (a8~a9) of pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? tbl allows a relative address be added to the current pc (r2+a ? r2), and contents of the ninth and tenth bits (a8~a9) of pc are not changed. thus, the computed jump can be on the second (or third, 4th) 256 locations on one program page. ? in case of EM78250, the most significant bit (a10) will be loaded with the content of bit ps0 in the status register (r3) upon the execution of a jmp, call, or any instruction which writes to r2. ? in case of em78450, the most significant bits (a10~a11) will be loaded with the contents of bits ps0~ps1 in the status register (r3) upon the execution of a jmp, call, or any instruction which writes to r2. fig. 3 program counter organization em78450 EM78250/450 call ret rttl reti pc a11 a10 a9 a8 a7~a0 stack 1 stack 2 stack 3 stack 4 stack 5 001 : hareware interrupt location 002 : software interrupt (int instruction) location fff : reset location 000 page 0 00 01 3ff 400 page 1 page 2 page 3 7ff 800 bff c00 fff 11 10 EM78250 em78450 * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 5 preliminary preliminary preliminary preliminary preliminary 12.16.1997 r3 (status register) 7 6 543210 gp ps1 ps0 t p z dc c bit 0 (c) carry flag bit 1 (dc) auxiliary carry flag bit 2 (z) zero flag. set to 1 if the result of an arithmetic or logic operation is zero. bit 3 (p) power down bit. set to 1 during power on or by a wdtc command and reset to 0 by a slep command. bit 4 (t) time-out bit. set to 1 by the slep and wdtc command, or during power up and reset to 0 by wdt timeout. bit 5 (ps0) page select bits. ps0~ps1 are used to preselect a program memory page. when executing ~6 (ps1) a jmp, call, or other instruction which causes the program counter to be changed (e.g. mov r2,a), ps0~ps1 are loaded into the 11th and 12th bits of the program counter, selecting one of the available program memory pages. note that ret (retl, reti) instruction does not change the ps0~ps1 bits. that is, the return will be always to the page from where the subroutine was called, regardless of the current setting of ps0~ps1 bits. ps1 bit is not used (read as 0) and cannot be modified in em78248. ps1 ps0 program memory page (address) 0 0 page 0 (000-3ff) (EM78250/450) 0 1 page 1 (400-7ff) (EM78250/450) 1 0 page 2 (800-bff) (em78450) 1 1 page 3 (c00-fff) (em78450) bit 7 (gp) general read/write bit. r4 (ram select register) ? bits 0~5 are used to select the registers (address: 00~3f) in the indirect addressing mode. ? bits 6~7 determine which bank is activated among the 4 banks. ? if no indirect addressing is used, the rsr can be used as an 8-bit wide general purpose read/write register. ? see the configuration of the data memory in fig. 4. r5~r8 (port 5 ~ port8) ? four 8-bit i/o registers, p74 and p76 read/write data from data pin. p75 and p77 read/write data from clk pin. r9 (port 9) ? 6-bit i/o registers. the high order 2 bits of r9 will be read as "0". * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 6 12.16.1997 preliminary preliminary preliminary preliminary preliminary ioc5 ioc6 ioc7 ioc8 ioc9 ioce iocf stack (5 levels) r0 r1(tcc) r2(pc) r3(status) r4(rsr) 00 01 02 03 04 r5(port5) r6(port6) r7(port7) r8(port8) r9(port9) ra rb rc rd re rf 16x8 commom register 11 10 01 00 31x8 bank register (bank 0) 31x8 bank register (bank 1) 31x8 bank register (bank 2) 31x8 bank register (bank 3) r3f 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 : : 1f 20 : : 3e 3f ra ~ r1f, r20~r3e (general purpose register) ? ra~r1f and r20~r3e (including banks 0~3) are general purpose registers. r3f (interrupt status register) 7 6 5 4 32 10 - - - - - - exif tcif ? bit 0 (tcif) tcc timer overflow interrupt flag. set when tcc timer overflows, reset in software. ? bit 1 (exif) external interrupt flag. set by falling edge on /int pin, reset in software. ? bits 2~~7 not used. ? 1 means interrupt request, 0 means non-interrupt. fig. 4 data memory configuration * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 7 preliminary preliminary preliminary preliminary preliminary 12.16.1997 ? r3f can be cleared by instruction and cannot be set by instruction. ? iocf is the interrupt mask register. ? note that reading r3f by instruction will get the result of logic and of r3f and iocf. special purpose registers a (accumulator) ? internal data transfer, or instruction operand holding. ? its not an addressable register. cont (control register) 76 5 43210 phen int - - pab psr2 psr1 psr0 bit 0 (psr0)~bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt bit 6 (int) interrupt enable flag which cannot be written by contw instruction. 0: interrupt masked by disi. 1 : interrupt enabled by eni/reti instruction. bit 7 (phen) i/o pin pull-high enable flag. 0: p60~p67 and p74~p75 and p90~p95 have internal pull-high. 1: pull-high is disabled. ? bits 0~3, 7 of cont register are readable and writable. ? bit 4,5 not used. ioc5 ~ ioc9 (i/o port control register) ? 1 put the relative i/o pin into high impedance, while 0 put the relative i/o pin as output. ? ioc5 ~ ioc9 are five i/o direction control registers. both p74 and p76, p75 and p77 avoid to do output pin at same time. only lower 6 bits are used in ioc9. iocd (pull-high control register) 76543210 s7 - - - pu9 pu8 pu6 pu5 * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 8 12.16.1997 preliminary preliminary preliminary preliminary preliminary ? pu5, pu6, pu8, pu9 default = 1, disable pull high. ? pu6, pu9 are "and" gating with phen, that is each one writed "0" will enable pull high. ? s7 select p70~p72 driving ability. 0 : normal output. 1 : leds driver. ioce (wdt control register) 76543210 - ode wte slpc roc - - wue bit 0 (wue) control bit used to enable wake-up function of p60~p67, p74~p75, p90~p91. 0: enable wake-up function 1: disable wake-up function wue bit is readable and writable. bit 3 (roc) roc is used for the r-option. setting roc to 1 will enable the status of r-option pin (p80, p81) to be read by the controller. clearing roc will disable the r-option function. if the r-option function is used, the user must connect the p81 pin or/and p80 pin to vss by a 560k w external resistor (rex). if rex is connected/disconnected, the status of p80(p81) will be read as 0/1 when roc is set to 1. refer to fig. 7(b). roc bit is readable and writable. bit 4 (slpc) this bit is set by hardware at the falling edge of wake-up signal and is cleared by software. slpc is used to control the operation of oscillator. the oscillator is disabled (oscillator is stopped, the controller enters the sleep2 mode) on high-to-low transition on slpc bit and is enabled (the controller is awakened from sleep2 mode) on low-to-high transition on slpc bit. in order to ensure the stable output of the oscillator, once the oscillator is disabled and is enabled again, there is a delay for approximately 18 ms (oscillator start-up timer, ost) before the next instruction of program being executed. the ost is always activated by wake- up from sleep mode whether the code option bit wtc is 0 or not. after waking up, the wdt is enabled if code option wtc is 1. the block diagram of sleep2 mode and wake-up caused by input triggered is depicted in fig. 5. slpc bit is readable and writeable. bit 5 (wte) control bit used to enable watchdog timer. wte bit is used only if the code option bit wtc is 1. if wtc bit is 1, then wdt is disabled/enabled by wte bit. 0: disable wdt 1: enable wdt wte bit is not used if the code option bit wtc is 0. that is, if wtc bit is 0, wdt is always disabled no matter what the wte bit is. wte bit is readable and writable. bit 6 (ode) open-drain control bit. 0: both p76 and p77 are normal i/o pins. 1: both p76 and p77 pins have open-drain output, but built-in internally. ode bit is readable and writable. bits 1,2,7 not used. * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 9 preliminary preliminary preliminary preliminary preliminary 12.16.1997 oscillator enable disable reset 1 d set clear from s/w 8 clk c l p r q q p60~p67 v cc v cc wue phen 8 p74~p75, p90~p95 wue wue wue fig. 5 block diagram of sleep mode and wake-up circuits on i/o ports iocf (interrupt mask register) 76543210 - - - - - - exie tcie bit 0(tcie) tcif interrupt enable bit. 0: disable tcif interrupt. 1: enable tcif interrupt. bit 1 (exie) exif interrupt enable bit 0: disable exif interrupt. 1: enable exif interrupt. bits 2~7 not used. ? individual interrupt is enabled by setting its associated control bit in iocf to 1. ? iocf register is readable and writable. tcc/wdt prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time and the pab bit of cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the prescale ratio. the prescaler will be cleared by instructions which write to tcc each time, when assigned to tcc mode. the wdt and prescaler, when assigned to wdt mode, will be cleared by the wdtc and slep instructions. fig. 6 depicts the circuit diagram of tcc/wdt. * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 10 12.16.1997 preliminary preliminary preliminary preliminary preliminary ? r1(tcc) is an 8-bit timer/counter. tcc will increase by one in every instruction cycle (without prescaler). ? the watchdog timer is a free running on-chip rc oscillator. the wdt will keep running even the oscillator driver has been turned off (i.e. in sleep mode). during the normal operation or the sleep mode, a wdt time- out (if enabled) will cause the device to reset. the wdt can be enabled or disabled at any time during the normal mode by software programming (if code option bit wtc is 1). refer to wte bit of ioce register. with no presacler, the wdt time-out period is approximately 18 ms. i/o ports the i/o registers, port 5 ~ port 9, are bi-directional tri-state i/o ports. p60~p67, p74~p75, p90~p91 can have internal pull-high and wake-up function by software control. p76~p77 can have open-drain output by software control. p80~p81 are the r-option pins which are enabled by software. while r-option function is used, p80~p81 are recommended to be used as output pins. during the period of r-option being enabled, p80~p81 must be programmed as input pins. if external resistor is connected to p80(p81) for r-option function, the current consumption should be noticed in the applications that low power are concerned. the i/o ports can be defined as input or output pins by the i/o control registers (ioc5~ioc9) under program control. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig. 7. note that the source is different between the reading path of input and output pin while reading the i/o port. fig. 6 block diagram of tcc and wdt pab pab pab wte (in ioce) wdt m u x m u x clk(=fosc/2) data bus tcc(r1) tcc overflow interrupt 8-bit counter psr0~psr2 8-to-1 mux mux wdt timeout sync 2 cycles 1 0 0 1 0 1 * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 11 preliminary preliminary preliminary preliminary preliminary 12.16.1997 fig. 7(a) the circuit of i/o port and i/o control register pcrd pcwr d p r q q clk c l pdwr pdrd d p r q q clk c l port m u x iod 0 1 pcrd pcwr d p r q q clk c l pdwr pdrd d p r q q clk c l port m u x iod 0 1 roc rex * weekly pull-up vcc * the rex is 560k ohm external resistor. fig. 7(b) the circuit of i/o port with r-option (p80,p81) * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 12 12.16.1997 preliminary preliminary preliminary preliminary preliminary fig. 8 the block diagram of reset of controller oscillator power-on reset wte wdt wdt timeout 18 ms reset clk d q clk clr vdd reset and wake-up the reset can be caused by (1) power on reset, or (2) wdt timeout. (if enabled) the device will be kept in a reset condition for a period of approx. 18ms (one oscillator start-up timer period) after the reset is detected. once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all 1. ? when power on, bits 5~6 of r3 and the upper 2 bits of r4 are cleared. ? all i/o port pins are configured as input mode (high-impedance state). ? the watchdog timer and prescaler are cleared. ? the watchdog timer is enabled if code option bit wtc is 1. ? the cont register is set to all 1 except bit 6 (int flag). ? bits 3,6 of ioce register are cleared, bits 0,4~5 of ioce register are set to 1. ? bits 0 of r3f and bits 0 of iocf registers are cleared. the sleep mode (power down mode) can be entered by executing the slep instruction (named as sleep1 mode). while entering sleep mode, the wdt (if enabled) is cleared but keeping running. the controller can be awakened by wdt timeout (if enabled), and it will cause the controller to be reset. the t and p flags of r3 can be used to determine the source of the reset (wake-up). in addition to the basic sleep1 mode, EM78250/450 has another sleep mode (caused by clearing slpc bit of ioce register, named as sleep2 mode). in the sleep2 mode, the controller can be awakened by (a) input triggered, refer to fig. 5. when wake-up, the controller will continue to execute program in-line. in this case, before entering sleep2 mode, the wake-up function of the trigger sources (p60~p67, p74~p75, and p90~p91) should be selected (e.g. input pin) and enabled (e.g. pull-high, wake-up control). one * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 13 preliminary preliminary preliminary preliminary preliminary 12.16.1997 caution should be noted is that after waking up, the wdt is enabled if code option bit wtc is 1. the wdt operation (to be enabled or disabled) should be appropriately controlled by software after waking up. (b) wdt time-out (if enabled). when wake-up, will cause the controller reset. interrupt the EM78250/450 has the following interrupts. (1) tcc overflow interrupt (2) external interrupt (/int) r3f is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 001h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the r3f register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. the flag in the interrupt status register (r3f) is set regardless of the status of its mask bit or the execution of eni instruction. note that reading r3f will get the output of logic and of r3f and iocf. refer to fig. 9. the reti instruction exits interrupt routine and enables the global interrupt (execution of eni instruction). when an interrupt is generated by int instruction (when enabled), causes the next instruction to be fetched from address 002h. fig. 9 interrupt input circuit interrupt eni/disi iod irqn . . irqm rfrd iocfwr p r d q q c l iocf clk iocfrd rfwr reset p r d q q c l clk r3f / irqn vcc * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 14 12.16.1997 preliminary preliminary preliminary preliminary preliminary instruction status binary hex hnemonic operation affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 15 preliminary preliminary preliminary preliminary preliminary 12.16.1997 instruction status binary hex hnemonic operation affected 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? a z 0 0100 01rr rrrr 04rr mov r,r r ? r z 0 0100 10rr rrrr 04rr coma r /r ? a z 0 0100 11rr rrrr 04rr com r /r ? r z 0 0101 00rr rrrr 05rr inca r r+1 ? a z 0 0101 01rr rrrr 05rr inc r r+1 ? rz 0 0101 10rr rrrr 05rr djza r r-1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n-1), r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n-1), r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1), r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1), r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) ? a(4-7), r(4-7) ? a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 16 12.16.1997 preliminary preliminary preliminary preliminary preliminary code option register the em78248/448 has one code option register which is not part of the normal program memory. the option bits cannot be accessed during normal program execution. 765432 10 - - - lvdd hlf ms ck2 wtc bit 0 (wtc): wdt option. 0 : wdt is always disabled. control bit wte in ioce is unused. 1 : wdt is enabled. wdt can be disabled/enabled by software programming. control bit wte in ioce register is used to disable/enable wdt. bit 1 (ck2): input clock divided by two selection. 0 : system clock is from oscillator clock directly. 1 : system clock is from oscillator clock divided by two. bit 2 (ms): oscillator type selection. 0 : rc type 1 : xtal type bit 3 (hlf): xtal frequency selection. 0 : low frequency, 32.768khz 1 : high frequency bit 4 (lvdd): operating voltage. 0 : 4v~6v 1 : 2v~4v bit 5~bit 7 : not used, must bt "0"s. * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 17 preliminary preliminary preliminary preliminary preliminary 12.16.1997 absolute maximum ratings items sym. condition rating temperature under bias t opr 0 c to 70 c storage temperature t str -65 c to 150 c input voltage v in -0.3v to +6.0v output voltage v o -0.3v to +6.0v ac electrical characteristics (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) input clk duty cycle dclk 45 50 55 % instruction cycle time tins rc type 500 dc ns (ck2="0") tcc input period ttcc (tins+20)/n* ns watchdog timer period twdt ta = 25 c18ms device reset hold period tdrh ta = 25 c18ms parameter symbol condition min. typ. max. unit * n= selected prescaler ratio. dc electrical characteristic (t a =0 c ~ 70 c, v dd =5.0v, v ss =0v) parameter sym. condition min. typ. max. unit input leakage current i il1 v in = v dd , v ss 1 m a input high voltage v ih 2.0 v input low voltage v il 0.8 v clock input high voltage v ihx osci 3.5 v clock input low voltage v ilx osci 1.5 v output high voltage v oh1 i oh = -12.0ma 2.4 v (port 5,6,8,9 and p74~p77) output high voltage v oh2 i oh = -10.0ma 2.4 v (p70~p72) output low voltage v ol1 i ol = 5.0ma 0.4 v (port 5,6,8,9 and p74~p77) (p70~p72, high drive mode) output low voltage v ol2 i ol = 10.0ma 3 v (p70~p72, low drive mode) pull-high current i ph pull-high active, input pin at v ss -250 -400 -500 m a power down current i sb all input and i/o pins at v dd , output 10 m a pin floating, wdt enabled operating supply current i cc1 reset='high', fosc=1.84324mhz (ck2="0"), output pin floating 3 ma * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 18 12.16.1997 preliminary preliminary preliminary preliminary preliminary * this specification are subject to be changed without notice. EM78250/450 8-bit micro-controller for consumer product 19 preliminary preliminary preliminary preliminary preliminary 12.16.1997 application circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vss /int data clk p90 p91 p92 p93 p94 p95 p50 p51 p52 p53 p54 p55 p56 p57 p80 p81 osco r-osci vdd p70 p71 p72 p67 p66 p65 p64 p63 p62 p61 p60 p87 p86 p85 p84 p83 p82 scroll num caps r7 r6 r5 r4 r3 r2 r1 r0 c15 c14 c13 c12 c11 c10 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 data clk c16 c17 u1 vcc 10 56k em78450 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 r0 110 045 115 035 036 116 117 041 099 104 083 060 r1 044 016 030 114 021 022 118 015 028 027 092 097 102 r2 058 001 112 113 006 007 119 120 013 012 076 075 085 080 r3 002 003 004 005 008 010 121 009 011 122 123 086 081 124 r4 017 018 019 020 023 025 024 026 091 096 101 016 125 r5 031 032 033 034 037 039 029 038 040 093 098 103 108 r6 064 057 046 047 048 049 052 054 043 053 042 090 095 100 126 r7 050 051 061 055 084 089 105 079 062 |
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